The manufacture of integrated circuits in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal wiring that forms interlevel and intralevel connections in a device is insulated by one or more dielectric layers in order to prevent crosstalk between the electrical pathways which can degrade device performance. A popular method of forming metal wiring is a damascene process in which a metal is deposited in an opening such as a via hole or a trench above a via in a dielectric layer. Usually, a conformal diffusion barrier layer is formed between the metal layer and dielectric layer to protect the metal from corrosion and oxidation and to prevent metal ions from migrating into the dielectric layer. The metal layer is typically planarized by a chemical mechanical polish (CMP) process.
Recent progress in forming metal interconnects includes lowering the resistivity of the metal by replacing aluminum with copper, decreasing the width of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulating materials to minimize capacitance coupling between the metal interconnects. Current technology involves forming vias and trenches that have sub-micron dimensions which are generally below 0.30 microns. Some leading edge devices have critical dimensions that are 100 nm or less. Although SiO2 which has a dielectric constant of about 4 has been widely used as a dielectric layer in older technologies, dielectric materials with a k value of less than about 3 are being implemented in new devices.
It should be noted that as the width of via holes or trench openings is shrinking in new technologies, the difficulty in forming a uniform thin diffusion barrier layer has resulted in adopting new techniques that include atomic layer deposition (ALD). For small holes, ALD is often preferred over chemical vapor deposition (CVD) methods for its improved gap filling capability and flexibility in composition by enabling a composite layer with three or more elements to be deposited in variety of monolayer sequences.
A recent advance in copper deposition as described in U.S. Pat. No. 6,420,258 involves a selective growth of copper by an electrochemical method on a conformal seed layer in a trench. The method reduces non-uniformity in metal CMP and thereby minimizes dishing at the top of the copper interconnect. However, a first CMP step that is used to remove the seed layer on the surface of the substrate can be difficult to control since the underlying diffusion barrier layer is frequently too thin to function as a good CMP stop.
A diffusion barrier cap is selectively deposited on a metal interconnect in U.S. Pat. No. 6,153,935 and provides corrosion protection and improved electromigration resistance. A barrier layer which is rhenium, rhodium, or ruthenium is formed on a copper interconnect in U.S. Pat. No. 6,441,492 and affords high resistance to Cu diffusion.
Dishing on a copper layer during a CMP step is avoided in U.S. Pat. No. 6,004,188 by employing a Ti/TiN sacrificial barrier layer on a dielectric layer, forming an opening in the dielectric layer, and depositing a Ta/TaN diffusion barrier liner in the opening prior to depositing a Cu layer. The copper level is lowered during a first CMP step that also removes the Ta/TaN above the dielectric layer at a relatively slow rate. Then a second CMP step planarizes the Cu while removing Ti/TiN at a similar rate. A sacrificial layer is also used in U.S. Pat. No. 6,417,095 and eliminates the need for a CMP step.
In U.S. Pat. No. 6,528,426, a SiC CMP stop layer is utilized to protect an underlying mechanically weak dielectric layer such as porous SiO2. Conformal nitride and Ta barrier layers are formed on the sidewalls of a dielectric layer in U.S. Pat. No. 6,509,267 to prevent Cu from being sputtered onto the dielectric layer during a via etch.
A carbon electroconductive layer is formed on the sidewalls and bottom of an opening in an amorphous C and F containing dielectric layer by a plasma treatment in U.S. Pat. No. 6,482,741. The electroconductive layer functions as a diffusion barrier and as a seed growth layer for a copper layer. However, the method does not provide a means for preventing Cu dishing.
Therefore, an improved method of forming copper wiring is needed which involves a good stop layer during a first CMP step to remove a copper seed layer from selective portions of the substrate. The method should also prevent dishing during a second CMP step to planarize a copper interconnect layer that is formed in an opening within a dielectric layer by an electrochemical process. The method should also be compatible with incorporation of a diffusion barrier layer between the copper layer and the dielectric layer.